Magnetic memory devices, such as magnetic random access memory (MRAM) devices, use magnetic memory cells to store information. Information is stored in a magnetic memory cell as the orientation of the magnetization of a free layer as compared to the orientation of the magnetization of a fixed or pinned layer. The magnetization of the free layer may be oriented parallel or anti-parallel to the fixed layer, representing either a logic “0” or a logic “1.” One type of memory cell, a magnetic tunnel junction (MTJ), consists of a pillar structure comprising a free layer and a fixed layer separated by a thin dielectric barrier (a tunnel barrier), which typically comprises Al2O3, MgO, or MgO sandwiched between thin layers of metal. The resistance of the memory cell depends on the direction of magnetization of the free layer relative to the direction of magnetization of the fixed layer. Thus, the state of the cell can be sensed by measuring its resistance.
Methods of reproducibly and reliably forming and contacting pillar structures in integrated circuits are presently undergoing intensive research. In the process integration of MRAM, for example, one of the challenging processing steps is the formation of a vertical contact between an MTJ pillar structure and an overlying conductive line. Unfortunately, this problem becomes progressively more difficult as MRAM is scaled to the smaller MTJ dimensions required for the 45 nm and 32 nm ground rule nodes.
Currently, there are two main MRAM integration approaches for forming vertical contacts between MTJ pillar structures and conductive lines. The first approach, illustrated in FIGS. 1A-1E, utilizes a via-level mask that is aligned and overlaid to an MTJ pillar structure. To achieve this, an MTJ pillar structure 100 is first patterned using a thin conductive hard mask 110 (e.g., TaN, TiN, or Al), as shown in FIG. 1A, and then encapsulated by an inter-layer dielectric (ILD) 120, as shown in FIG. 1B. Then, via lithography is performed and a via 130 is etched into the ILD, landing on the MTJ pillar structure, as shown in FIG. 1C. This is followed by the patterning of a metallization level, achieved by etching a trench 140 in the shape of a line that overlies the via, as shown in FIG. 1D. Finally, the structure is metallized in order to form a vertical contact 150 between a conductive line 160 and the MTJ pillar structure, as shown in FIG. 1E. Even though this approach works well for relatively large MTJ pillar structures (e.g., those with widths or diameters greater than about 100 nm), it has limitations as MTJ sizes become smaller. Overlay errors make alignment of the via to the MTJ pillar structure extremely difficult as the size of the MTJ shrinks. Hence, the via-based approach is not useful for MRAM scaling to 45 nm and 32 nm nodes.
The second approach utilizes a tall conductive hard mask (e.g., TaN, TiN, or Al) as a vertical contact, as illustrated in FIGS. 2A-2E. To form this thick hard mask on top of an MTJ pillar structure, the MTJ pattern is first transferred into a thick conductive layer that is deposited on top of magnetic layers. This patterned layer is then used as a hard mask to etch the magnetic structure. The resultant MTJ pillar structure 200 with tall hard mask 210 is shown in FIG. 2A. It is then encapsulated with dielectric layers 220 and 230, as shown in FIG. 2B, and planarized, as shown in FIG. 2C. Next, a trench 240 in the shape of a line is etched into the dielectric layers in such a manner that the hard mask protrudes into the trench, a shown in FIG. 2D. Finally the trench is filled with metal, which allows the tall hard mask to serve as a vertical contact between a conductive line 250 and the MTJ pillar structure, as shown in FIG. 2E. Because the size of the hard mask scales with the size of the MTJ pillar structure, the approach provides a path for forming vertical contacts to small MTJ structures (e.g., those below 100 mm in width or diameter). However, patterning the MTJ using a tall conductive hard mask is problematic due to the formation of sidewall redeposition, shown as feature 260 in the figures, that shorts the junctions, and foot structures due to shadowing during etching. Furthermore, the planarization step usually introduces non-uniformity, which is transferred into the etch process used to form the trench for the conductive line. As a result, the trench may be too shallow, resulting in an open circuit, or the trench may be too deep, etching to the base of the MTJ pillar structure at position 270 and causing a short circuit, as shown in FIGS. 2D and 2E. Due to these problems, the tall hard mask approach does not provide a straight-forward path for the formation of contacts for MRAM scaling.
For the foregoing reasons, there is a need for reliable and reproducible methods of forming contacts to sub-100 nm pillar structures in integrated circuits.